1. Field of the Invention
The invention relates to a clock signal generator and method thereof, in particular, to be used for adjustment.
2. Related Art
In the process of data transmission, it is essential to keep the output data signal in synchronization with the system clock. However, when the data or clock signal is transmitted via the printed-circuit-board (PCB), it is usually coupled to generate noise. Further, the optimal latch phase is shortened due to the jitter of the signal itself and the time skew caused by the different lengths of the signal wires on the PCB. That is, the latch duration between the data and the data strobe signal (DOS) is reduced. Therefore, the generation of a better and appropriate phase for latching the data, especially for the application in high-speed circuits, has become an extremely important task in the research of this field.
With regard to the clock signal generator of the prior art, please refer to FIG. 1, wherein the conventional clock signal generator comprises a delay locked loop (DLL) 110, a delay module 120, and a multiplexer 130. The delay lock loop 110 has a voltage controlled delay line (VCDL) 118 formed by a plurality of voltage controlled delay cells 119 connected in series. The delay module 120 has a plurality of VCDLs. When the system clock CKi is inputted to the DLL 110, the DLL 110 generates a voltage control signal Vc for supplying to each VCDL of the delay module 120. The voltage controlled delay cell 122 of the VCDL of the delay module 120 is substantially the same as the voltage controlled delay cell 119 in the DLL 110. That is, these voltage controlled delay cells 119, 122 have substantially the same characteristics relative to the voltage control signal Vc. As such, the output clock CKo is kept latched on the system clock CKi, and then the output data signal and the system clock is maintained in synchronization is achieved.
Furthermore, as shown in FIG. 2, the DLL 110 may be replaced by a phase locked loop (PLL) 210. Referring to FIG. 2, in this case, the clock signal generator comprises: a PLL 210, a delay module 220 and a multiplexer 230. The PLL 210 has a voltage controlled oscillator (VCO) 218.
However, the delay time of the voltage controlled delay cells of the delay module are controlled by the voltage control signal VC. Thus, the DLL or PLL must consistently consume power. Further, the areas occupied by the voltage controlled delay cells of the delay module are much larger.